The fabrication of integrated circuits (ICs) involves the formation of features on a substrate that make up circuit components, such as transistors, resistors and capacitors. The devices are interconnected, enabling the ICs to perform the desired functions. Interconnections are formed by forming contacts and conductive lines in an interconnecting dielectric layer (ICD) using, for example, damascene techniques. A damascene structure, for example, includes a via or contact hole in a lower portion and a trench which is generally wider than the contact hole in an upper portion. The via serves as a contact to a device while the trench contains the conductive line for connecting the device to, for example, other devices.
To form the features and interconnections, layers are repeatedly deposited on the substrate and patterned as desired using lithographic techniques. Such techniques generally use an exposure source to project an image from a mask onto a photoresist layer formed on the surface of the substrate. The exposure source illuminates the resist layer, exposing it with the desired pattern. Developing the resist exposes portions of the underlying layer, which are removed by etching while the unexposed portions are protected and remain intact.
However, designers are faced with numerous challenges regarding interconnections as technology progresses beyond deep ultraviolet (DUV) lithography (<193 nm). For example, striations in contact holes are a common phenomenon due to softness of resist used in such type of lithography. Striations can result in shorts as well as other problems. Additionally, due to the softer photoresist being used, a larger photoresist budget or thicker photoresist layer is required. This reduces the depth of focus of the lithography, which can result in shorts or opens due to misalignment of the contact holes. These problems decrease critical dimension (CD) control which reduces the process window for forming interconnections, thus lowering yields and increasing manufacturing cost.
From the foregoing discussion, it is desirable to provide improved interconnections in ICs.